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preliminary gs81302t06/11/20/38e-450/400/375/333/300 144mb sigmaddr tm -ii+ burst of 2 sram 450 mhz?300 mhz 1.8 v v dd 1.8 v or 1.5 v i/o 165-bump bga commercial temp industrial temp rev: 1.01a 6/2010 1/32 ? 2009, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? 2.5 clock latency ? simultaneous read and write sigmaddr tm interface ? jedec-standard pinout and package ? double data rate interface ? byte write controls sampled at data-in time ? burst of 2 read and write ? on-die termination (odt) on data (d), byte write ( bw ), and clock (k, k ) inputs ? 1.8 v +100/?100 mv core power supply ? 1.5 v or 1.8 v hstl interface ? pipelined read operation ? fully coherent read and write pipelines ? zq pin for programmable output drive strength ? data valid pin (qvld) support ? ieee 1149.1 jtag-compliant boundary scan ? 165-bump, 15 mm x 17 mm, 1 mm bump pitch bga package ? rohs-compliant 165-bump bga package available sigmaddr-ii ? family overview the gs81302t06/11/20/38e are built in compliance with the sigmaddr-ii+ sram pinout standard for common i/o synchronous srams. they are 150,994,944-bit (144mb) srams. the gs81302t06/11/20/38e sigmaddr-ii+ srams are just one element in a family of low power, low voltage hstl i/o srams designe d to operate at the speeds needed to implement ec onomical high performance networking systems. clocking and addressing schemes the gs81302t06/11/20/38e sigmaddr-ii+ srams are synchronous devices. they employ two input register clock inputs, k and k . k and k are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. because common i/o sigmaddr-ii+ rams always transfer d a ta in two packets, a0 is internally set to 0 for the first read or write transfer, and automati cally incremented by 1 for the next transfer. because the lsb is tied off internally, the address field of a sigmaddr-ii+ b2 ram is always one address pin less than the advertised index depth (e.g., the 8m x 18 has a 4m addressable index). parameter synopsis -450 -400 -375 -333 -300 tkhkh 2.2 ns 2.5 ns 2.66 ns 3.0 ns 3.3 ns tkhqv 0.37 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns 165-bump, 15 mm x 17 mm bga 1 mm bump pitch, 11 x 15 bump array bottom view
4m x 36 sigmaddr- ii+ sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa r/ w bw2 k bw1 ld sa sa cq b nc dq27 dq18 sa bw3 k bw0 sa nc (288mb sa) nc dq8 c nc nc dq28 v ss sa nc sa v ss nc dq17 dq7 d nc dq29 dq19 v ss v ss v ss v ss v ss nc nc dq16 e nc nc dq20 v ddq v ss v ss v ss v ddq nc dq15 dq6 f nc dq30 dq21 v ddq v dd v ss v dd v ddq nc nc dq5 g nc dq31 dq22 v ddq v dd v ss v dd v ddq nc nc dq14 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc dq32 v ddq v dd v ss v dd v ddq nc dq13 dq4 k nc nc dq23 v ddq v dd v ss v dd v ddq nc dq12 dq3 l nc dq33 dq24 v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc dq34 v ss v ss v ss v ss v ss nc dq11 dq1 n nc dq35 dq25 v ss sa sa sa v ss nc nc dq10 p nc nc dq26 sa sa qvld sa sa nc dq9 dq0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm 2 body?1 mm bump pitch notes: 1. bw0 controls writes to dq0:dq8; bw1 controls writes to dq9:dq17; bw2 controls writes to dq18:dq26; bw3 controls writes to dq27:dq35 2. pin b9 is the expansion address. preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 2/32 ? 2009, gsi technology
8m x 18 sigmaddr- ii+ sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa r/ w bw1 k sa ld sa sa cq b nc dq9 nc sa nc (288mb sa) k bw0 sa nc nc dq8 c nc nc nc v ss sa nc sa v ss nc dq7 nc d nc nc dq10 v ss v ss v ss v ss v ss nc nc nc e nc nc dq11 v ddq v ss v ss v ss v ddq nc nc dq6 f nc dq12 nc v ddq v dd v ss v dd v ddq nc nc dq5 g nc nc dq13 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq4 nc k nc nc dq14 v ddq v dd v ss v dd v ddq nc nc dq3 l nc dq15 nc v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc nc v ss v ss v ss v ss v ss nc dq1 nc n nc nc dq16 v ss sa sa sa v ss nc nc nc p nc nc dq17 sa sa qvld sa sa nc nc dq0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm 2 body?1 mm bump pitch notes: 1. bw0 controls writes to dq0:dq8; bw1 controls writes to dq9:dq17 2. pin b5 is the expansion address. preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 3/32 ? 2009, gsi technology
16m x 9 sigmaddr- ii+ sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa r/ w nc k sa ld sa sa cq b nc nc nc sa nc/sa (288mb) k bw0 sa nc nc dq4 c nc nc nc v ss sa sa sa v ss nc nc nc d nc nc nc v ss v ss v ss v ss v ss nc nc nc e nc nc dq5 v ddq v ss v ss v ss v ddq nc nc dq3 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc nc dq6 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq2 nc k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc dq7 nc v ddq v ss v ss v ss v ddq nc nc dq1 m nc nc nc v ss v ss v ss v ss v ss nc nc nc n nc nc nc v ss sa sa sa v ss nc nc nc p nc nc dq8 sa sa qvld sa sa nc nc dq0 r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm 2 body?1 mm bump pitch notes: 3. bw0 controls writes to dq0:dq8. 4. pin b5 is the expansion address. preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 4/32 ? 2009, gsi technology
16m x 8 sigmaddr- ii+ sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa r/ w nw1 k sa ld sa sa cq b nc nc nc sa nc/sa (288mb) k nw0 sa nc nc dq3 c nc nc nc v ss sa sa sa v ss nc nc nc d nc nc nc v ss v ss v ss v ss v ss nc nc nc e nc nc dq4 v ddq v ss v ss v ss v ddq nc nc dq2 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc nc dq5 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq1 nc k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc dq6 nc v ddq v ss v ss v ss v ddq nc nc dq0 m nc nc nc v ss v ss v ss v ss v ss nc nc nc n nc nc nc v ss sa sa sa v ss nc nc nc p nc nc dq7 sa sa qvld sa sa nc nc nc r tdo tck sa sa sa odt sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm 2 body?1 mm bump pitch notes: 1. nw0 controls writes to dq0:dq3; nw1 controls writes to dq4:dq7. 2. pin b5 is the expansion address. preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 5/32 ? 2009, gsi technology
pin description table symbol description type comments sa synchronous address inputs input ? r/ w synchronous read/write input high: read low: write bw0 ? bw3 synchronous byte writes input active low ld synchronous load pin input active low k input clock input active high k input clock input active low tms test mode select input ? tdi test data input input ? tck test clock input input ? tdo test data output output ? v ref hstl input reference voltage input ? zq output impedance matching input input ? mcl must connect low ? ? dq data i/o input/output three state doff disable dll when low input active low cq output echo clock output ? cq output echo clock output ? v dd power supply supply 1.8 v nominal v ddq isolated output buffer supply supply 1.8 v or 1.5 v nominal v ss power supply: ground supply ? qvld q valid output output ? odt on-die termination input ? nc no connect ? ? preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 6/32 ? 2009, gsi technology notes: 1. nc = not connected to die or any other pin 2. when zq pin is directly connected to v ddq , output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 7/32 ? 2009, gsi technology background common i/o srams, from a system architectur e point of view, are attractiv e in read dominated or bl ock transfer applications. therefore, the sigmaddr-ii+ sram interf ace and truth table are optimized for burs t reads and writes. common i/o srams are unpopular in applications where alternating reads and writes are needed because bus turn around delays can cut high speed common i/o sram data bandwidth in half. burst operations read and write operations are "b urst" operations. in every case where a read or write command is accepted by the sram, it will respond by issuing or accepting two beat s of data, executing a data transfer on subsequent rising edges of k and k , as illustrated in the timing diagrams. it is not possible to stop a burst once it st arts. two beats of data are alwa ys transferred. this means th at it is possible to load new addresses ev ery k clock cycle. addresses can be loaded less often, if intervening de select cycles are inse rted. deselect cycles chip deselect commands are pipelined to the same degree as read commands. this means th at if a deselect command is applied to the sram on the next cycle after a read command captured by the sr am, the device will complete the two beat read data transfer and then execute the deselect command, returning the output drivers to high-z. a high on the ld pin prevents the ram from loading read or write command inputs and puts the ram into dese lect mode as soon as it completes all outstanding burst transfer operations. sigmaddr-ii+ burst of 2 sram read cycles the sram executes pipelined reads. the status of the address, ld and r/ w pins are evaluated on the ri sing edge of k. the read command ( ld low and r/ w high) is clocked into the sram by a rising edge of k. sigmaddr-ii+ burst of 2 sram write cycles the status of the address, ld and r/ w pins are evaluated on the rising edge of k. the sram executes "late write" data transfers. data in is due at the device inputs on the rising edge of k following the rising edge of k clock used to clock in the write com mand ( ld and r/ w low) and the write address. to complete the remaining beat of the burst of two write transfer, the sram captures data in on the next rising edge of k , for a total of two tran sfers per address load.
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 8/32 ? 2009, gsi technology power-up sequence for sigmaddr-ii+ srams for compatibility across all vendors it is recommended that sigmaddr-ii+ srams must be powered-up in a specific sequence in order to avoid undefined operations. power-up sequence 1. power-up and maintain doff at low state. 1a. apply v dd . 1b. apply v ddq . 1c. apply v ref (may also be applied at the same time as v ddq ). 2. after voltages are within speci fication range, and clocks (k, k ) are stablized, change doff to high. 3. an additional 2048 clock cycles are required to lock the dll after it has been enabled. note: the dll m a y be reset by driving the doff pin low or by stopping the k clocks for at least 30 ns. 2048 cycles of clean k clocks are always required to relock the dll after it has been stabilized. dll constraints the dll synchronizes to either k clock. th ese clocks shou ld have low phase jitter (t kvar ). ? the dll cannot operate at a frequenc y lower than that specified by the t khkh maximum specification for the desired operating clock frequency. ? if the incoming clock is not stablized when dll is enabled, the dll may lo ck on the wrong frequency and cause undefined errors or failure s during the initial stage. special functions byte write and nybble write control byte write enable pins are sampled at the same time that data in is sam pl ed. a high on the byte write enable pin associated wit h a particular byte (e.g., bw0 controls d0?d8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. an y or all of the byte write enable pins may be driven high or low during the data in sample times in a write sequence. each write enable command and write address loaded into the ram provid e s the base address for a 2-beat data transfer. the x18 version of the ram, for example, may write 36 bits in associatio n with each address loaded. any 9-bit byte may be masked in any write sequence. nybble write (4-bit) control is implemented on the 8-bit-wide version of t he device. for the x8 version of the device, ?nybble write enable? and ? nwx ? may be substituted in all the discussion above. resulting write operation byte 1 d0?d8 byte 2 d9?d17 byte 3 d0?d8 byte 4 d9?d17 written unchanged unchanged written beat 1 beat 2 example x18 ram write sequence using byte write enables data in sample time bw0 bw1 d0?d8 d9?d17 beat 1 0 1 data in don?t care beat 2 1 0 don?t care data in
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 9/32 ? 2009, gsi technology flxdrive-ii output driver impedance control hstl i/o sigmaddr-ii+ srams are supplied with programmable im pedance output drivers. the zq pin must be connected to v ss via an external resistor, rq, to allow th e sram to monitor and adjust its output driver impedance. the value of rq must be 5x the value of the desired ram output impedance. the allowable range of rq to guarantee impeda nce matching continuously is between 175 and 350 . periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. the sram?s output impeda nce circuitry compensates for drifts in supply voltage and temperature. a clock cycle counter periodi cally triggers an impedance evaluation, resets and coun ts again. each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. the output driver is implemented with discrete binary weighted impedance steps. input termination impedance control these sigmaddr-ii+ srams are suppli ed with programmable input termination on data (dq), byte write ( bw ), and clock (k, k ) input receivers. input terminati on can be enabled or disabled via the odt pin (6r). when the odt pin is tied low (or left floating?the pin has a small pull-down resistor), input termination is disabled. when the odt pi n is tied high, input terminat ion is enabled. termination impedance is programmed via the same rq resistor (connected between the zq pin and v ss ) used to program output driver impedance, and is nominally rq*0.6 thevenin-equivalent when rq is between 175 and 250 . periodic readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same manner as for driver impedance (see above). notes: 1. when odt = 1, byte write ( bw ), and clock (k, k ) input termination is always enabled. consequently, bw , k, k inputs should always be driven high or low; they should never be tri- stated (i.e., in a high-z state) . if the inputs are tri-stated, the input termination will pull the signal to v ddq /2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver to enter a meta-stable state and preven t the sram from operating within specification. 2. when odt = 1, dq input termination is enabled during w rite and nop operations, and disabled during read operations. specifically, dq input termination is disabled 0.5 cycles before the sram enables its dq drivers and starts driving valid read data, and remains disabled until 0.5 cycles after the sram stops driving valid read data and disables its dq drivers; dq input termination is enabled at all other times. consequently, the sram controller should disable its dq input termination, enable its dq drivers, and drive dq in puts (high or low) during write and nop operations. and, it should enable its dq input termination and disable its dq drivers during read opera tions. care should be taken during write or nop -> read transitions, and during read -> nop transitions, to minimize the time during which one device (sram or sram controller) has enabled its dq input termination while the other device has not yet enabled its dq driver. otherwise, the input termination will pull the signal to v ddq /2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver to enter a meta- stable state and prevent the sram from operating within specification.
common i/o sigmaddr-ii+ burs t of 2 sram truth table k n ld r/ w dq operation a + 0 a + 1 1 x hi-z / * hi-z / * deselect 0 0 d@k n+1 d@ k n+1 write 0 1 q@ k n+2 q@k n+3 read notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?v ? = input ?valid?; ?x? = inpu t ?don?t care?. 2. d1 and d2 indicate the first and second pieces of w r ite data transferred during write operations. 3. q1 and q2 indicate the first and second pieces of read data tra nsferred d uring read operations. 4. when on-die termination is disabled (odt = 0), dq drivers are disabl ed (i.e., dq pins are tri-st ated) for one cycle in respon se to nop and w rite commands, 2.5 cycles after the command is sampled. 5. when on-die termination is enabled (odt = 1), dq drivers ar e disabled for one cycle in response to nop and w r ite commands, 2. 5 cycles after the command is sampled. the state of the dq pins during that time (denoted by ?*? in the table above) is determine d by the state of the dq input termination. see the input termination impedance control section for more information. preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 10/32 ? 2009, gsi technology
burst of 2 byte write clock truth table bw bw current operation d d k (t n + 1 ) k (t n + 1? ) k (t n ) k (t n + 1 ) k (t n + 1? ) t t write dx stored if bwn = 0 in both data transfers d1 d2 t f write dx stored if bwn = 0 in 1st data transfer only d1 x f t write dx stored if bwn = 0 in 2nd data transfer only x d2 f f write abort no dx stored in either data transfer x x notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. 2. if one or more bwn = 0, then bw = ?t?, else bw = ?f?. burst of 2 nybble write clock truth table nw nw current operation d d k (t n + 1 ) k (t n + 1? ) k (t n ) k (t n + 1 ) k (t n + 1? ) t t write dx stored if nwn = 0 in both data transfers d1 d2 t f write dx stored if nwn = 0 in 1st data transfer only d1 x f t write dx stored if nwn = 0 in 2nd data transfer only x d2 f f write abort no dx stored in either data transfer x x notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. 2. if one or more nwn = 0, then nw = ?t?, else nw = ?f?. preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 11/32 ? 2009, gsi technology
x36 byte write enable ( bwn ) truth table bw0 bw1 bw2 bw3 d0?d8 d9?d17 d18?d26 d27?d35 1 1 1 1 don?t care don?t care don?t care don?t care 0 1 1 1 data in don?t care don?t care don?t care 1 0 1 1 don?t care data in don?t care don?t care 0 0 1 1 data in data in don?t care don?t care 1 1 0 1 don?t care don?t care data in don?t care 0 1 0 1 data in don?t care data in don?t care 1 0 0 1 don?t care data in data in don?t care 0 0 0 1 data in data in data in don?t care 1 1 1 0 don?t care don?t care don?t care data in 0 1 1 0 data in don?t care don?t care data in 1 0 1 0 don?t care data in don?t care data in 0 0 1 0 data in data in don?t care data in 1 1 0 0 don?t care don?t care data in data in 0 1 0 0 data in don?t care data in data in 1 0 0 0 don?t care data in data in data in 0 0 0 0 data in data in data in data in x18 byte write enable ( bwn ) truth table bw0 bw1 d0?d8 d9?d17 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in x8 nybble write enable ( nwn ) truth table nw0 nw1 d0?d3 d4?d7 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 12/32 ? 2009, gsi technology
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 13/32 ? 2009, gsi technology burst of 2 state diagram power-up nop load new address ddr read ddr write load read write load load load load notes: 1. the internal address burst counter is a 1 bit counter (i.e., when first address is a0, next internal burst address is a0+1). 2. ?read? refers to read active status with r/w = high, ?write? refers to write inactive status with r/w = low. 3. ?load? refers to read new address active status with ld = low, ?load ? refers to read new address inactive status with ld = high. load
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 14/32 ? 2009, gsi technology recommended oper ating conditions power supplies parameter symbol min. typ. max. unit supply voltage v dd 1.7 1.8 1.9 v i/o supply voltage v ddq 1.4 ? v dd v reference voltage v ref v ddq /2 ? 0.05 ? v ddq /2 + 0.05 v note: . the power supplies need to be powered up simult aneously or in the fo llowing sequence: v dd , v ddq , v ref , followed by signal inputs. the power down sequence must be the reverse. v ddq must not exceed v dd . operating temperature parameter symbol min. typ. max. unit ambient temperature (commercial range versions) t a 0 25 70 c ambient temperature (industrial range versions) t a ?40 25 85 c absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 2.9 v v ddq voltage in v ddq pins ?0.5 to v dd v v ref voltage in v ref pins ?0.5 to v ddq v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 2.9 v max.) v v in voltage on other input pins ?0.5 to v ddq +0.5 ( 2.9 v max.) v v tin input voltage (tck, tms, tdi) ?0.5 to v ddq +0.5 ( 2.9v max.) v i in input current on any pin +/?100 ma dc i out output current on any i/o pin +/?100 ma dc t j maximum junction temperature 125 o c t stg storage temperature ?55 to 125 o c note: permanent damage to the device may occur if the absolute maximu m ratings are exceeded. operati on should be re stricted to recomm ended operating conditions. exposure to conditi ons exceeding the recommended operating condi tions, for an extended period of time, ma y affect reliability of this component.
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 15/32 ? 2009, gsi technology hstl i/o dc input characteristics parameter symbol min max units notes input reference voltage v ref v ddq /2 ? 0.05 v ddq /2 + 0.05 v ? input high voltage v ih1 v ref + 0.1 v ddq + 0.3 v 1 input low voltage v il1 ?0.3 v ref ? 0.1 v 1 input high voltage v ih2 0.7 * v ddq v ddq + 0.3 v 2,3 input low voltage v il2 ?0.3 0.3 * v ddq v 2,3 notes: 1. parameters apply to k, k , sa, dq, r/ w , bw , ld during normal operation and jtag boundary scan testing. 2. parameters apply to doff , odt during normal operation an d jtag boundary scan testing. 3. parameters apply to zq during jtag boundary scan testing only. hstl i/o ac input characteristics parameter symbol min max units notes input reference voltage v ref v ddq /2 ? 0.08 v ddq /2 + 0.08 v ? input high voltage v ih1 v ref + 0.2 v ddq + 0.5 v 1,2,3 input low voltage v il1 ?0.5 v ref ? 0.2 v 1,2,3 input high voltage v ih2 v ddq ? 0.2 v ddq + 0.5 v 4,5 input low voltage v il2 ?0.5 0.2 v 4,5 notes: 1. v ih(max) and v il(min) apply for pulse widths less than one-quarter of the cycle time. 2. input rise and fall times myust be a minimum of 1 v/ns, and within 10% of each other. 3. parameters apply to k, k , sa, dq, r/ w , bw , ld during normal operation and jtag boundary scan testing. 4. parameters apply to doff , odt during normal operation an d jtag boundary scan testing. 5. parameters apply to zq during jtag boundary scan testing only. capacitance o c, f = 1 mh z , v dd = 1.8 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf output capacitance c out v out = 0 v 6 7 pf clock capacitance c clk v in = 0 v 5 6 pf note: this parameter is sample tested. (t a = 25
ac test conditions parameter conditions input high level 1.25 v input low level 0.25 v max. input slew rate 2 v/ns input reference level 0.75 v output reference level v ddq /2 note: test conditions as specified with output loading as shown unl ess otherwise noted. preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 16/32 ? 2009, gsi technology dq vt = v ddq /2 50 rq = 250 (hstl i/o) v ref = 0.75 v ac test load diagram input and output leakage characteristics parameter symbol test conditions min. max input leakage current (except mode pins) i il v in = 0 to v ddq ?2 ua 2 ua doff i il doff v in = 0 to v ddq ?20 ua 2 ua odt i ilodt v in = 0 to v ddq ?2 ua 20 ua output leakage current i ol output disable, v out = 0 to v ddq ?2 ua 2 ua
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 17/32 ? 2009, gsi technology hstl i/o output driver dc electrical characteristics parameter symbol min. max. units notes output high voltage v oh1 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 1, 3 output low voltage v ol1 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 2, 3 output high voltage v oh2 v ddq ? 0.2 ? v 4, 5 output low voltage v ol2 ? 0.2 v 4, 6 notes: 1. i oh = (v ddq /2) / (rq/5) +/? 15% @ v oh = v ddq /2 (for: 175 rq 275 ). 2. i ol = (v ddq /2) / (rq/5) +/? 15% @ v ol = v ddq /2 (for: 175 rq 275) . 3. parameter tested with rq = 250 and v ddq = 1.5 v 4. 0 rq ? 5. i oh = ?1.0 ma 6. i ol = 1.0 ma
operating currents parameter symbol test conditions -450 -400 -375 -333 -300 notes 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85 c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c operating current (x36): ddr i dd v dd = max, i out = 0 ma cycle time t khkh min 1165 ma 1175 ma 1050 ma 1060 ma 995 ma 1005 ma 900 ma 910 ma 820 ma 830 ma 2, 3 operating current (x18): ddr i dd v dd = max, i out = 0 ma cycle time t khkh min 1055 ma 1065 ma 955 ma 1005 ma 900 ma 910 ma 815 ma 825 ma 745 ma 755 ma 2, 3 operating current (x9): ddr i dd v dd = max, i out = 0 ma cycle time t khkh min 1055 ma 1065 ma 955 ma 1005 ma 900 ma 910 ma 815 ma 825 ma 745 ma 755 ma 2, 3 operating current (x8): ddr i dd v dd = max, i out = 0 ma cycle time t khkh min 1055 ma 1065 ma 955 ma 1005 ma 900 ma 910 ma 815 ma 825 ma 745 ma 755 ma 2, 3 standby current (no p ): ddr i sb1 device deselected, i out = 0 ma, f = max, all inputs 0.2 v or v dd ? 0.2 v 235 ma 245 ma 225 ma 235 ma 220 ma 230 ma 210 ma 220 ma 200 ma 210 ma 2, 4 notes: 1. power measured with output pins floating. 2. minimum cycle, i out = 0 ma 3. operating current is calculated with 5 0% read cycles and 5 0% write cycles. 4. standby current is only after all pending r ead and write burst operations are complete d. preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 18/32 ? 2009, gsi technology
ac electrical characteristics parameter symbol -450 -400 -375 -333 -300 units notes min max min max min max min max min max clock k, k clock cycle time t khkh 2.2 8.4 2.5 8.4 2.66 8.4 3.0 8.4 3.3 8.4 ns tk variable t kvar ? 0.15 ? 0.2 ? 0.2 ? 0.2 ? 0.2 ns 4 k, k clock high pulse width t khkl 0.4 ? 0.4 ? 0.4 ? 0.4 ? 0.4 ? cycle k, k clock low pulse width t klkh 0.4 ? 0.4 ? 0.4 ? 0.4 ? 0.4 ? cycle k to k high t kh k h 0.94 ? 1.06 ? 1.13 ? 1.28 ? 1.4 ? ns k to k high t k hkh 0.94 ? 1.06 ? 1.13 ? 1.28 ? 1.4 ? ns dll lock time t klock 32k ? 32k ? 32k ? 32k ? 32k ? cycle 5 k static to dll reset t kreset 30 ? 30 ? 30 ? 30 ? 30 ? ns output times k, k clock high to data output valid t khqv ? 0.37 ? 0.45 ? 0.45 ? 0.45 ? 0.45 ns k, k clock high to data output hold t khqx ?0.37 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns k, k clock high to echo clock valid t khcqv ? 0.37 ? 0.45 ? 0.45 ? 0.45 ? 0.45 ns k, k clock high to echo clock hold t khcqx ?0.37 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns cq, cq high output valid t cqhqv ? 0.15 ? 0.2 ? 0.2 ? 0.2 ? 0.2 ns cq, cq high output hold t cqhqx ?0.15 ? ?0.2 ? ?0.2 ? ?0.2 ? ?0.2 ? ns cq, cq high to qlvd t qvld ?0.15 0.15 ?0.2 0.2 -0.2 -0.2 -0.2 0.2 cq phase distortion t cqh cq h t c q hcqh 0.85 ? 1.0 ? 1.08 ? 1.25 ? 1.40 ? ns k clock high to data output high-z t khqz ? 0.37 ? 0.45 ? 0.45 ? 0.45 ? 0.45 ns k clock high to data output low-z t khqx1 ?0.37 ? ?0.45 ? ?0.45 ? ?0.45 ? ?0.45 ? ns setup times address input setup time t avkh 0.275 ? 0.4 ? 0.4 ? 0.4 ? 0.4 ? ns 1 control input setup time (r/ w ) t ivkh 0.275 ? 0.4 ? 0.4 ? 0.4 ? 0.4 ? ns 2 control input setup time ( bwx ) t ivkh 0.22 ? 0.28 ? 0.28 ? 0.28 ? 0.28 ? ns 3 data input setup time t dvkh 0.22 ? 0.28 ? 0.28 ? 0.28 ? 0.28 ? ns hold times address input hold time t khax 0.275 ? 0.4 ? 0.4 ? 0.4 ? 0.4 ? ns 1 control input hold time (r/ w ) t khix 0.275 ? 0.4 ? 0.4 ? 0.4 ? 0.4 ? ns 2 control input hold time ( bwx ) t khix 0.22 ? 0.28 ? 0.28 ? 0.28 ? 0.28 ? ns 3 data input hold time t khdx 0.22 ? 0.28 ? 0.28 ? 0.28 ? 0.28 ? ns notes: 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. control singles are r/ w , ld . 3. control singles are bw0 , bw1 and ( bw2 , bw3 for x36). 4. clock phase jitter is the variance from cloc k rising edge to the next expected clock rising edge. 5. v dd slew rate must be less than 0.1 v dc per 50 ns for dll lock retention. dll lock time begins once v dd and input clock are stable. preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 19/32 ? 2009, gsi technology
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 20/32 ? 2009, gsi technology read-write k-based timing diagram noop read noop noop write read read noop noop write write a1 a2 a3 a4 a5 a6 d d d d tqvld tqvld tdvkh tkhdx tkhqv tkhqx tkhqx tkhqv tkhdx tdvkh tkhz tkhqx tklz tkhix tivkh tkhix tivkh tkhax tavkh k k addr ld w r/ qvld dq cq cq
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 21/32 ? 2009, gsi technology read-write cq-based timing diagram noop read noop noop write read read noop noop write write a1 a2 a3 a4 a5 a6 q1 q1+1 d2 d2+1 q3 q3+1 q4 q4+1 d5 d5+1 d6 tcqhqx tcqlqv tcqhqv tcqlqx tcqlqx tqvld tcqhqv tcqlqv tcqhqx tqvld tdvkh tkhdx tkhdx tdvkh tkhix tivkh tkhix tivkh tkhax tavkh k k addr ld w r/ dq cq cq qvld
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 22/32 ? 2009, gsi technology jtag port operation overview the jtag port on this ram operates in a manner that is compliant with ieee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag). the jtag port input inte rface levels scale with v dd . the jtag output drivers are powered by v dd . disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unles s clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the fa llin g edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state ma chine. an undriven tms input will produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed be tween tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controller state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the fa llin g edge of tck. this is the output side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ie ee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap cont roller is also reset automaticly at power-up. jtag port registers overview the various jtag registers, refered to as tes t access port or ta p registers, are selected (one at a time) via the sequences of 1s and 0s applied to tms as tck is strobed. each of the tap regist ers is a serial shift register that captures serial input data o n the rising edge of tck and pushes serial data out on the next falling edge of tck. when a register is selected, it is placed betwe en the tdi and tdo pins. instruction register the instruction register holds the instructi ons that are executed by the ta p controller when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. th e instruction register can be lo aded when it is placed betwee n the tdi and tdo pins. the instruction register is automatically preloa ded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed th rough the ram?s jtag port to another device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pin s . the flip flops are then daisy chained togeth er so the levels found can be shifted seri ally out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip fl ops (always set to a logic 1). the relationship between t he device pins and the bits in the boundary scan register is described in the scan order table following. the boundary scan
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 23/32 ? 2009, gsi technology register, under the control of the tap contro ller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. sample-z, sample/preload and extest instructions can be us ed to activate the boundary scan register. instruction register id code register boundary scan register 012 0 31 30 29 12 0 bypass register tdi tdo tms tck test access port (tap) controller 108 1 0 control signals jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction re gister. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when th e controller is moved into shift- dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. id register contents see bsdl model gsi technology jedec vendor id code presence register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x x x x x x x x x x 0 0 0 1 1 0 1 1 0 0 1 1
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 24/32 ? 2009, gsi technology tap controller instruction set overview there are two classes of instructions defined in the standard 114 9.1-1 990; the standard (public) instructions, and device speci fic (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on th is device may be used to monitor all inpu t and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in captur e-ir s t ate the two least significant bits of the instruction regi ster are loaded wit h 01. when the controller is moved to the shift-ir state the instruction register is placed between tdi and tdo. in this state the de sired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions , the tap executes newly loaded instruct ions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 11 1 jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass regi ster is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facili - tate testing of other devices in the scan path.
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 25/32 ? 2009, gsi technology sample/preload sample/preload is a standard 1149.1 mandatory public in stru ction. when the sample / preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. boundary scan regist er locations are not associated with an input or i/o pin, and are loaded with the default stat e identified in the boundary s can chain table at the end of th is section of the datasheet. beca use the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inputs w ill not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set-up plus hold time (tts plus tth) . the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary s can register. moving the contro ller to shift-dr state then places the boundary scan register between the tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instru ction register is loaded with all logic 0s. the extest command does not block or override th e ram?s input pins; therefore, the ram?s internal state is still determined by its input pins. typically, the boundary scan re gister is loaded with the desired pattern of data with the sample/preload command. then the extest command is used to outp ut the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling edge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest command. when the extest instruc - tion is selected, the sate of all the ram?s input and i/o pins, as well as the defau lt values at scan register locations not as so - ciated with a pin, are transfer red in parallel into the boundary scan regist er on the rising edge of tck in the capture-dr state, the ram?s output pins drive out the value of the boundar y scan register location with which each output pin is associ - ated. idcode the idcode instruction causes the id rom to be loaded into the id registe r when the controller is in capture-dr mode and places the id register between the tdi a nd tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the ins truction register, all ram outputs are forced to an inactiv e drive state (high- z) and the boundary scan register is connected between tdi and t do when the tap controller is moved to the shift-dr state.
jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan register between tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 gsi 011 gsi private instruction. 1 sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 gsi 110 gsi private instruction. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state. preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 26/32 ? 2009, gsi technology jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes test port input low voltage v ilj ? 0.3 0.3 * v dd v 1 test port input high voltage v ihj 0.7 * v dd v dd +0.3 v 1 tms, tck and tdi input leakage current i inhj ? 300 1 ua 2 tms, tck and tdi input leakage current i inlj ? 1 100 ua 3 tdo output leakage current i olj ? 1 1 ua 4 test port output high voltage v ohj v dd ? 0.2 ? v 5, 6 test port output low voltage v olj ? 0.2 v 5, 7 test port output cmos high v ohjc v dd ? 0.1 ? v 5, 8 test port output cmos low v oljc ? 0.1 v 5, 9 notes: 1. input under/overshoot voltage must be ? 1 v < v i < v ddn +1 v not to exceed v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj v in v ddn 3. 0 v v in v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v dd supply. 6. i ohj = ? 2 ma 7. i olj = + 2 ma 8. i ohjc = ?100 ua 9. i oljc = +100 ua
notes: 1. include scope and jig capacitance. 2. test conditions as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v dd /2 tdo v dd /2 50 30pf * jtag port ac test load * distributed test jig capacitance preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 27/32 ? 2009, gsi technology jtag port timing diagram tth tts ttkq tth tts tth tts ttklttkl ttkhttkh ttkcttkc tck tdi tms tdo parallel sram input jtag port ac electri cal characteristics parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 28/32 ? 2009, gsi technology package dimensions?165-bump fpbga (package e) a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 a1 corner top view a1 corner bottom view 1.0 1.0 10.0 1.0 1.0 14.0 150.05 170.05 a b 0.20(4x) ?0.10 ?0.25 c c a b m m ?0.40~0.60 (165x) c seating plane 0.15 c 0.36~0.46 1.50 max.
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 29/32 ? 2009, gsi technology ordering information?gsi sigmaddr-ii+ sram org part number 1 type package speed (mh z) t a 2 16m x 8 gs81302t06e-450 sigmaddr-ii+sram 165-bump bga 450 c 16m x 8 gs81302t06e-400 sigmaddr-ii+sram 165-bump bga 400 c 16m x 8 gs81302t06e-375 sigmaddr-ii+sram 165-bump bga 375 c 16m x 8 gs81302t06e-333 sigmaddr-ii+sram 165-bump bga 333 c 16m x 8 gs81302t06e-300 sigmaddr-ii+sram 165-bump bga 300 c 16m x 8 gs81302t06e-450i sigmaddr-ii+sram 165-bump bga 450 i 16m x 8 gs81302t06e-400i sigmaddr-ii+sram 165-bump bga 400 i 16m x 8 gs81302t06e-375i sigmaddr-ii+sram 165-bump bga 375 i 16m x 8 gs81302t06e-333i sigmaddr-ii+sram 165-bump bga 333 i 16m x 8 gs81302t06e-300i sigmaddr-ii+sram 165-bump bga 300 i 16m x 8 gs81302t06ge-450 sigmaddr-ii+sram rohs-compliant 165-bump bga 450 c 16m x 8 gs81302t06ge-400 sigmaddr-ii+sram rohs-compliant 165-bump bga 400 c 16m x 8 gs81302t06ge-375 sigmaddr-ii+sram rohs-compliant 165-bump bga 375 c 16m x 8 gs81302t06ge-333 sigmaddr-ii+sram rohs-compliant 165-bump bga 333 c 16m x 8 gs81302t06ge-300 sigmaddr-ii+sram rohs-compliant 165-bump bga 300 c 16m x 8 gs81302t06ge-450i sigmaddr-ii+sram rohs-compliant 165-bump bga 450 i 16m x 8 gs81302t06ge-400i sigmaddr-ii+sram rohs-compliant 165-bump bga 400 i 16m x 8 gs81302t06ge-375i sigmaddr-ii+sram rohs-compliant 165-bump bga 375 i 16m x 8 gs81302t06ge-333i sigmaddr-ii+sram rohs-compliant 165-bump bga 333 i 16m x 8 gs81302t06ge-300i sigmaddr-ii+sram rohs-compliant 165-bump bga 300 i 16m x 9 gs81302t11e-450 sigmaddr-ii+sram 165-bump bga 450 c 16m x 9 gs81302t11e-400 sigmaddr-ii+sram 165-bump bga 400 c 16m x 9 gs81302t11e-375 sigmaddr-ii+sram 165-bump bga 375 c 16m x 9 gs81302t11e-333 sigmaddr-ii+sram 165-bump bga 333 c 16m x 9 gs81302t11e-300 sigmaddr-ii+sram 165-bump bga 300 c 16m x 9 gs81302t11e-450i sigmaddr-ii+sram 165-bump bga 450 i 16m x 9 gs81302t11e-400i sigmaddr-ii+sram 165-bump bga 400 i 16m x 9 gs81302t11e-375i sigmaddr-ii+sram 165-bump bga 375 i 16m x 9 gs81302t11e-333i sigmaddr-ii+sram 165-bump bga 333 i 16m x 9 GS81302T11E-300I sigmaddr-ii+sram 165-bump bga 300 i 16m x 9 gs81302t11ge-450 sigmaddr-ii+sram rohs-compliant 165-bump bga 450 c notes: 1. for tape and reel add the character ?t? to the end of the part number . example: gs81302txxe-300t. 2. c = commercial temperature range. i = industrial t emperature range.
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 30/32 ? 2009, gsi technology 16m x 9 gs81302t11ge-400 sigmaddr-ii+sram rohs-compliant 165-bump bga 400 c 16m x 9 gs81302t11ge-375 sigmaddr-ii+sram rohs-compliant 165-bump bga 375 c 16m x 9 gs81302t11ge-333 sigmaddr-ii+sram rohs-compliant 165-bump bga 333 c 16m x 9 gs81302t11ge-300 sigmaddr-ii+sram rohs-compliant 165-bump bga 300 c 16m x 9 gs81302t11ge-450i sigmaddr-ii+sram rohs-compliant 165-bump bga 450 i 16m x 9 gs81302t11ge-400i sigmaddr-ii+sram rohs-compliant 165-bump bga 400 i 16m x 9 gs81302t11ge-375i sigmaddr-ii+sram rohs-compliant 165-bump bga 375 i 16m x 9 gs81302t11ge-333i sigmaddr-ii+sram rohs-compliant 165-bump bga 333 i 16m x 9 gs81302t11ge-300i sigmaddr-ii+sram rohs-compliant 165-bump bga 300 i 4m x 18 gs81302t20ge-450 sigmaddr-ii+sram 165-bump bga 450 c 4m x 18 gs81302t20ge-400 sigmaddr-ii+sram 165-bump bga 400 c 4m x 18 gs81302t20ge-375 sigmaddr-ii+sram 165-bump bga 375 c 4m x 18 gs81302t20ge-333 sigmaddr-ii+sram 165-bump bga 333 c 4m x 18 gs81302t20ge-300 sigmaddr-ii+sram 165-bump bga 300 c 4m x 18 gs81302t20ge-450i sigmaddr-ii+sram 165-bump bga 450 i 4m x 18 gs81302t20ge-400i sigmaddr-ii+sram 165-bump bga 400 i 4m x 18 gs81302t20ge-375i sigmaddr-ii+sram 165-bump bga 375 i 4m x 18 gs81302t20ge-333i sigmaddr-ii+sram 165-bump bga 333 i 4m x 18 gs81302t20ge-300i sigmaddr-ii+sram 165-bump bga 300 i 4m x 18 gs81302t20ge-450 sigmaddr-ii+sram rohs-compliant 165-bump bga 450 c 4m x 18 gs81302t20ge-400 sigmaddr-ii+sram rohs-compliant 165-bump bga 400 c 4m x 18 gs81302t20ge-375 sigmaddr-ii+sram rohs-compliant 165-bump bga 375 c 4m x 18 gs81302t20ge-333 sigmaddr-ii+sram rohs-compliant 165-bump bga 333 c 4m x 18 gs81302t20ge-300 sigmaddr-ii+sram rohs-compliant 165-bump bga 300 c 4m x 18 gs81302t20ge-450i sigmaddr-ii+sram rohs-compliant 165-bump bga 450 i 4m x 18 gs81302t20ge-400i sigmaddr-ii+sram rohs-compliant 165-bump bga 400 i 4m x 18 gs81302t20ge-375i sigmaddr-ii+sram rohs-compliant 165-bump bga 375 i 4m x 18 gs81302t20ge-333i sigmaddr-ii+sram rohs-compliant 165-bump bga 333 i 4m x 18 gs81302t20ge-300i sigmaddr-ii+sram rohs-compliant 165-bump bga 300 i 2m x 36 gs81302t38e-450 sigmaddr-ii+sram 165-bump bga 450 c 2m x 36 gs81302t38e-400 sigmaddr-ii+sram 165-bump bga 400 c 2m x 36 gs81302t38e-375 sigmaddr-ii+sram 165-bump bga 375 c ordering information?gsi sigm addr-ii+ sram (continued) org part number 1 type package speed (mhz) t a 2 notes: 1. for tape and reel add the character ?t? to the end of the part number. example: gs81302txxe-300t. 2. c = commercial temperature range. i = industrial temperature range.
preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 31/32 ? 2009, gsi technology 2m x 36 gs81302t38e-333 sigmaddr-ii+sram 165-bump bga 333 c 2m x 36 gs81302t38e-300 sigmaddr-ii+sram 165-bump bga 300 c 2m x 36 gs81302t38e-450i sigmaddr-ii+sram 165-bump bga 450 i 2m x 36 gs81302t38e-400i sigmaddr-ii+sram 165-bump bga 400 i 2m x 36 gs81302t38e-375i sigmaddr-ii+sram 165-bump bga 375 i 2m x 36 gs81302t38e-333i sigmaddr-ii+sram 165-bump bga 333 i 2m x 36 gs81302t38e-300i sigmaddr-ii+sram 165-bump bga 300 i 2m x 36 gs81302t38ge-450 sigmaddr-ii+sram rohs-compliant 165-bump bga 450 c 2m x 36 gs81302t38ge-400 sigmaddr-ii+sram rohs-compliant 165-bump bga 400 c 2m x 36 gs81302t38ge-375 sigmaddr-ii+sram rohs-compliant 165-bump bga 375 c 2m x 36 gs81302t38ge-333 sigmaddr-ii+sram rohs-compliant 165-bump bga 333 c 2m x 36 gs81302t38ge-300 sigmaddr-ii+sram rohs-compliant 165-bump bga 300 c 2m x 36 gs81302t38ge-450i sigmaddr-ii+sram rohs-compliant 165-bump bga 450 i 2m x 36 gs81302t38ge-400i sigmaddr-ii+sram rohs-compliant 165-bump bga 400 i 2m x 36 gs81302t38ge-375i sigmaddr-ii+sram rohs-compliant 165-bump bga 375 i 2m x 36 gs81302t38ge-333i sigmaddr-ii+sram rohs-compliant 165-bump bga 333 i 2m x 36 gs81302t38ge-300i sigmaddr-ii+ sram rohs-compliant 165-bump bga 300 i ordering information?gsi sigm addr-ii+ sram (continued) org part number 1 type package speed (mhz) t a 2 notes: 1. for tape and reel add the character ?t? to the end of the part number. example: gs81302txxe-300t. 2. c = commercial temperature range. i = industrial temperature range.
sigmaddr-ii+ sram revision history file name format/content description of changes 81302txxe_r1 ? creation of datasheet 81302txxe_r1.01 content ? added on-die termination feature ? added x6, x11 pinout ? (rev1.01a: removed cq reference from sample-z section in jt ag t ap instruction set summary) preliminary gs81302t06/11/20/38e-450/400/375/333/300 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01a 6/2010 32/32 ? 2009, gsi technology

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